CMOS logic circuits are typically designed to consume minimal power when operating, particularly when there are no logic transitions within the logic circuit. For standard CMOS logic circuits, minimal power consumption is realized because the CMOS logic devices do not draw significant current when there are no logic transitions. However, complex programmable logic devices (CPLDs) typically do not exhibit low power consumption, based on the use of wired logic gates within the CPLD architecture. As described below, the use of wired logic gates causes CPLDs to exhibit significant power consumption, even during static conditions. As a result, CPLDs experience increased power consumption not only as a function of switching frequency, but also as a function of the states of the wired logic gates.
Power consumption within a CPLD is calculated by multiplying the current drawn by the CPLD times the voltage drop across the CPLD. It is common to isolate three distinct regions of a device for the sake of simplicity when calculating power consumption, namely, the input circuitry, the output circuitry and the interior circuitry. The input and output circuitry is not of concern, because the CPLD input and output circuitry uses conventional CMOS digital circuitry. As a result, the CPLD input and output circuitry does not contribute greatly to the power consumption of the device.
However, the interior circuitry of a CPLD differs substantially from the transistor structure found in CMOS digital circuits such as common logic chips, field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs). The interior circuitry of CPLDs is substantially composed of non-volatile programmable logic cells. More specifically, the interior circuitry of most CPLDs is built from EPROM, EEPROM or FLASH memory elements that are used to form wired logic gates inside the chip.
FIG. 1 is a circuit diagram of a basic wired logic gate (i.e., a wired AND gate) of the type typically found in a CPLD. Wired AND gate 10 includes sense amplifier 1, bit line 2, resistors 3 and 4, and n-channel non-volatile memory transistors 5-7, which are switched by input signals A, B and C. These input signals can be provided, for example, by input logic pins, by internal logic variables, or by internal state variables received from binary flip flops. Wired AND gate 10 operates as follows. Sense amplifier 1 is powered by the V.sub.CC supply voltage. Resistor 3 is connected between the V.sub.CC voltage supply terminal and bit line 2. Resistor 4 is connected between bit line 2 and the ground supply terminal. If none of transistors 5-7 is in a conductive state, then a relatively high voltage drop is developed across resistor 4, thereby maintaining bit line 2 at a voltage V.sub.BITLINE.sbsb.--.sub.HI. When the voltage of bit line 2 is equal to the voltage V.sub.BITLINE.sbsb.--.sub.HI, bit line 2 is said to be in a logic high state. The voltage V.sub.BITLINE.sbsb.--.sub.HI is greater than the trip point voltage V.sub.TRIP required to cause sense amplifier 1 to provide a logic high output signal (OUT).
In general, a non-volatile memory transistor includes a floating gate, which can be programmed to store either a negative charge or a neutral charge. When programmed to store a negative charge, a non-volatile memory transistor is said to be in an erased state. When programmed to store a neutral charge, a non-volatile memory transistor is said to be in a programmed state. When a non-volatile memory transistor is in the erased state, the negative charge stored by the floating gate prevents the non-volatile memory transistor from turning on regardless of the voltage applied to the control gate of the non-volatile memory transistor. When a non-volatile memory transistor is in the programmed state, the neutral charge stored by the floating gate allows the non-volatile memory transistor to be controlled by the voltage applied to the control gate of the non-volatile memory transistor.
Thus, if non-volatile memory transistors 5-7 are in the erased state, then these transistors 5-7 will not turn on, regardless of the voltages of the applied A, B and C signals. Under these conditions, bit line 2 will always be in the logic high state, regardless of the A, B and C signals.
When in the programmed state, non-volatile memory transistors 5-7 will turn on if the respective signals A, B and C are asserted at logic high levels, and will turn off if the respective signals A, B and C are asserted at logic low levels. When non-volatile memory transistors 5-7 are in the programmed state, wired AND gate 10 becomes a three-input AND gate. Under these conditions, if each of the A, B and C signals have logic low values (i.e., the A, B and C signals have logic high values), then transistors 5-7 are each turned off, and bit line 2 is in the logic high state. However, if any of the A, B and C signals has a logic high value, then the corresponding transistor(s) will turn on. For example, if the A signal has a logic high value and the B and C signals have logic low values, then transistor 5 is turned on and transistors 6 and 7 are turned off. As a result, the current from bit line 2 to the ground supply terminal is shared between resistor 4 and transistor 5. The turned on transistor 5 causes the voltage on bit line 2 to be reduced to a voltage level V.sub.BITLINE.sbsb.--.sub.LO, which is less than the trip point voltage V.sub.TRIP of sense amplifier 1. When the voltage of bit line 2 is equal to V.sub.BITLINE.sbsb.--.sub.LOW, bit line 2 is said to be in a logic low state.
FIG. 2 is a graph showing the voltages V.sub.CC, V.sub.TRIP, V.sub.BITLINE.sbsb.--.sub.HI and V.sub.BITLINE.sbsb.--.sub.LO. As illustrated in FIG. 2, bit line 2 is always maintained at a voltage greater than zero Volts. As a result, wired AND gate 10 will always draw current, regardless of the state of wired AND gate 10. The current drawn by wired AND gate 10 is a primary source of power consumption in a CPLD. Table 1 below summarizes conventional currents drawn by wired AND gate 10.
TABLE 1 ______________________________________ High-Speed Low-Power Logic Gate Logic Gate ______________________________________ Current Drawn 180 .mu.A 20 .mu.A For V.sub.BITLINE.sbsb.--.sub. HI Current Drawn 350 .mu.A 200 .mu.A For V.sub.BITLINE.sbsb.--.sub.LO ______________________________________
Note that Table 1 defines two variations of wired AND gate 10, namely, a high-speed variation and a low-power variation. The high-speed variation is implemented by selecting resistor 3 to have a relatively small resistance. The low-power variation is implemented by selecting resistor 3 to have a relatively large resistance.
Referring to Table 1, it is seen that in both the high-speed and low-power variations, much less current is drawn by wired AND gate 10 when bit line 2 is in the logic high state. However, many bit lines of a CPLD are typically in the logic low state, thereby increasing the power consumption of the CPLD. From a power consumption standpoint, it would therefore be desirable to maximize the number of bit lines in the logic high state. However, it is difficult to constrain the exterior signals in order to maintain a high number of logic high bit lines.
In general, a CPLD is a configurable digital logic device that includes an array of wired AND gates which are configured to generate a plurality of product terms, and a plurality of OR gates which are coupled to receive the product terms from the wired AND gates. CPLDs are often configured to implement state machines for digital logic circuits. In general, a state machine defines the states and state transitions of a digital logic circuit. Each state is represented by a binary number, which is stored by a set of flip flops within the CPLD. State machines are well known to those skilled in the art.
The binary state assignments for state machines that control digital logic circuits have been a source of research for several decades. The primary focus has been to determine state assignments which can be systematically applied, and which optimize circuit behavior. Optimization of circuit behavior can include such items as minimizing the required amount of external logic, improving operating speed or minimizing the required number of cell inputs. The most common state assignments include binary state assignments, Gray code state assignments and one-hot state assignments. These common state assignments are described briefly below.
State assignments are typically stored in flip flops within a CPLD. The input and output terminals of the flip flops (along with other logic circuitry) are coupled in a manner which provides the desired states and state transitions. The contents of the flip flops define the present state of the state machine.
When using binary state assignments, consecutive states are assigned consecutive binary numbers. A state machine having 2.sup.N binary state assignments is typically implemented using N flip flops. For example, a state machine having eight binary state assignments is typically implemented using three flip flops. Table 2 shows how eight binary state assignments are implemented using three flip flops.
TABLE 2 ______________________________________ 1st Flip Flop 2nd Flip Flop 3rd Flip Flop ______________________________________ State 1 0 0 0 State 2 0 0 1 State 3 0 1 0 State 4 0 1 1 State 5 1 0 0 State 6 1 0 1 State 7 1 1 0 State 8 1 1 1 ______________________________________
When using Gray code state assignments, the consecutive states are assigned binary numbers that differ by a minimum number of bit changes. A state machine having 2.sup.N Gray code state assignments is typically implemented using N flip flops. For example, a state machine having eight Gray code state assignments can be implemented using three flip flops. Table 3 shows how eight Gray code state assignments are implemented using three flip flops.
TABLE 3 ______________________________________ 1st Flip Flop 2nd Flip Flop 3rd Flip Flop ______________________________________ State 1 0 0 0 State 2 0 0 1 State 3 0 1 1 State 4 0 1 0 State 5 1 1 0 State 6 1 1 1 State 7 1 0 1 State 8 1 0 0 ______________________________________
When using one-hot state assignments, each state is assigned a dedicated binary bit, and only one bit is high at any given time. A state machine having N one-hot state assignments is implemented using N flip flops. For example, a state machine having eight one-hot state assignments is implemented using eight flip flops. Table 4 shows how eight one-hot state assignments are implemented using eight flip flops.
TABLE 4 ______________________________________ 1st 2nd 3rd 4th 5th 6th 7th 8th Flip Flip Flip Flip Flip Flip Flip Flip Flop Flop Flop Flop Flop Flop Flop Flop ______________________________________ State 1 1 0 0 0 0 0 0 0 State 2 0 1 0 0 0 0 0 0 State 3 0 0 1 0 0 0 0 0 State 4 0 0 0 1 0 0 0 0 State 5 0 0 0 0 1 0 0 0 State 6 0 0 0 0 0 1 0 0 State 7 0 0 0 0 0 0 1 0 State 8 0 0 0 0 0 0 0 1 ______________________________________
Because of power usage, it would be desirable to have a method of operating a CPLD that maximizes the number of bit lines maintained in a logic high state.